The present invention relates to data processing systems. In particular, the present invention relates to data processing systems in which data can be overlaid from one memory onto another memory.
Prior art embedded controllers support various memories, including memories on and off the chip. For example, some embedded controllers have a FLASH memory block as well as an SRAM memory block. Sometimes it is desired to change data in the FLASH memory during normal operation of the embedded controller. For example, for an embedded controller used as a controller for an engine (or other electromechanical device), various parameters, which are stored in the FLASH memory, may need to be changed in order to properly tune the engine. Since FLASH memory may not be readily programmed during normal operation of the embedded controller, prior art embedded controllers use an overlay scheme to overlay data from the SRAM memory block onto the FLASH memory.
Prior art overlay schemes have various problems. One problem relates to data transfer time. Data transfer time is defined as the elapsed time between when the bus master requests data and when the data is available and all access terminating signals are received. It is critical to maintain the same data transfer time when accessing the FLASH memory or the overlaid FLASH region. Prior art overlay schemes may not maintain this same data transfer rate for on-chip or off-chip FLASH memory. As a result, the embedded controller may not operate in the same way for data placed in the overlay as compared to when the same data is placed in the FLASH memory.
Another problem is that the overlay schemes used in the prior art can only overlay entire memory blocks. In other words, if the embedded controller has 512 Byte SRAM memory modules used by the overlay scheme, the entire 512 Bytes of any one module must be overlaid. It would be desirable to selectively overlay portions of the memory modules, as opposed to overlaying the entire module. It would also be desirable to select the size of the overlay portions.
Another problem with prior art overlay schemes is that in order to have multiple overlay blocks, multiple memory modules are needed, each with its own separate bus interface unit (BIU). Having multiple BIUs requires separate circuitry for each BIU which takes up space on a chip.